FPGA Hardware Engineer - Internship

Do you want to tackle the biggest questions in finance with near infinite compute power at your fingertips?

G-Research is a leading quantitative research and technology firm, with offices in London and Dallas. We are proud to employ some of the best people in their field and to nurture their talent in a progressive, adaptable and highly stimulating culture where world-beating ideas are cultivated and rewarded.

This role is based in our new Soho Place office – opened in 2023 - in the heart of Central London and home to our Research Lab.

The Role

• 31st March 2025 or 30th June 2025 to 19th September 2025
• 09:00 – 17:30 working hours
• Based in Central London

We are currently seeking the brightest students to join our 12 or 24-week summer internships between their penultimate and final year of study, finishing in September.

Joining G-Research as an intern within our ResEng function will enable you to develop your knowledge of working with successful legacy systems as they are modernised; a highly sought-after skill.

This is a fantastic opportunity for an innovative, intellectually curious student to build world-class software. This challenging and satisfying software development role will also include delivering improvements to our production code.

The Low Latency Engineering (LLE) Group is responsible for a low-latency trading system that is a critical part of a global investment platform. The group includes teams responsible for market-data, order-entry and order-execution functions.

This FPGA Engineering role offers the chance to work at the forefront of ultra-low latency trading, developing and optimizing hardware solutions that drive critical trading performance. You'll collaborate closely developers to design cutting-edge systems, ensuring high-speed execution in a progressive and fast-paced environment. This is an opportunity to make a significant impact on trading strategies through innovative hardware solutions.

Key responsibilities of the role include:

• RTL HDL development principally in SystemVerilog
• Writing automated test benches
• Building Continuous Delivery pipelines for all components
• Some software development in python and C++

Who are we looking for?

The successful candidate will be an enthusiastic and capable engineer who is able to solve real-world problems in HDL. They will be able to work flexibly and pro-actively and be able to make complex systems work and to debug them when they don't.The ideal candidate will have:

• Great HDL development skills in SystemVerilog
• Excellent system analysis and debugging skills
• Some knowledge of scripting in a language like Python or Perl
• Effective communication skills with both technical and non-technical people
• Some software development skills in C or C++
• Financial experience is useful but not required

Induction and training

Successful candidates will gain an in-depth introduction to the world of technology within finance, as well as extensive introductions to the internal workings of the business.

You will be paired with an experienced Engineer who will mentor you through your time with us. All interns will have access to numerous training courses, including online learning licenses to hone your technical skills and soft skill training.

Perks of the role

• Highly competitive compensation
• Informal dress code and excellent work/life balance
• 30 days’ holiday pro-rata
• 9% company pension contributions
• Opt-in private health insurance
• Monthly company events
• Central London office close to five stations and six tube lines